Integrated circuits (ICs) frequently include circuits that operate at different logical high voltage levels. For example, input/output (I/O) circuits frequently operate at a higher voltage than circuits in the core of the IC. A higher voltage can be desirable at the I/O pads to interface properly with other ICs operating at a higher voltage, and to drive the heavily loaded output signals at an acceptable speed. A lower voltage can be desirable in the core of the IC to reduce power consumption and to enable the use of smaller transistors, thereby reducing the overall die size. Thus, many situations exist where an IC includes signals that are generated by a circuit at a first power (e.g., high) level than provided to another circuit operating at a second (e.g., higher or lower) logical high voltage level. To accommodate these situations, level shifter circuits are commonly used.
There have been many trials in prior arts to speed up operation and reduce the power consumption (esp. lower-to-higher voltage level shifter). However, they do not consider leakage currents which can happen during a power-up sequence. Having a proper power-up sequence in a system-on-chip (SOC) is one of the critical design issues since it is related with transistor break-down and/or leakage current resulting in problems. As fabrication processes become nano scale and more sub-systems are combined into a single chip, many power domains are included in SOCs and/or ICs and designers need to prevent silicon break down and reduce leakage current from interfaces. Level shifters are one of the most critical circuits in SOC designs because it operates as an interface circuit between two different power domains.
FIG. 1 is an example of a conventional lower-to-higher voltage level shifter. VDDL and VDDH depict power supplies for lower voltage and higher voltage, respectively. Normally, VDDL and VDDH have 1.0V˜1.2V and 1.8V˜2.5V, respectively. INV1 and INV2 are CMOS inverters which consist of one PMOS transistor and one NMOS transistor.
FIG. 2 shows a CMOS inverter for INV1 20 and INV2 22 of FIG. 1. P0 and N0 should be core devices for high speed operation with VDDL. FIG. 1 depicts that cross coupled logic 10 is used to convert lower to higher voltage and transistors 12-18 N1, N2, P1 and P2 should be I/O devices in order to endure voltage stress from VDDH. There have been a lot of trials to improve speed and minimize the power consumption from the design but they deal with normal operation after power-up sequence. A few prior arts also show the technique to protect power sequence for level shifter but they affect operating speed or area because of cascode structure.
A drawback of the design is evident during the power-up sequence. Generally, there is a time delay between VDDL and VDDH at the power-up sequence because they are generated from different voltage regulators or have different loads. VDDH either leads VDDL or lags behind VDDL. The duration between VDDH and VDDL can be a few milliseconds.
FIG. 3 is the case when VDDH leads VDDL in a power up sequence with a time delay, Td. In this case, the leakage current is observed from VDDH to ground during Td because X and Y in FIG. 1 become high impedance nodes. High impedance node means that it has an unknown voltage value. P1, P2, N1 and N2 are turned on under the unknown values at X and Y. The total leakage is not negligible when the system has lots of level shifters and it is an issue in mobile applications. The way to block the leakage current in a power-up sequence is to make sure that VDDL leads VDDH to avoid high impedance nodes at X and Y. It is a sort of system design restriction.
FIG. 4 is an example of a prior art level shifter 400 to block the leakage current of FIG. 1 at power-up sequence. Cascode transistors 402 and 404 P3 and P4 are added in the cross coupled logic and connected between PMOS and NMOS transistors P1, N1 and P2, N2. Also, the additional input, ENB enable, is needed to control the cascode transistors P3 and P4. Alternatively P3 and P4 can be replaced with NMOS transistors and placed between input NMOS (N1 and N2) and ground using EN which is an inverted signal from ENB.
The timing relationship among signals is shown in FIG. 5. ENB becomes high before both VDDH and VDDL are turned on and returns to low after both VDDH and VDDL are turned on. The voltage level of ENB should be either equal to or higher than VDDH so that ENB can prevent the leakage current from VDDH to ground during Td.
Comparing FIG. 1, there are also a few drawbacks with respect to the design of FIG. 4. Firstly, additional devices (P3 and P4) not only increase the circuit size but also degrade performance of level shifter due to turn-on resistor and parasitic capacitance added between P1 and N1 or P2 and N2.
Secondly, an extra start-up signal is needed, ENB, which has a new timing requirement with VDDH and VDDL. In general, ENB can be implemented from the first power-up supply on the system. FIG. 6 depicts VDDR is the first power-up supply which is related with start-up operation in the system. ENB is turned on along with VDDR and off after VDDH and VDDL are turned on. However, ENB can not be directly generated from VDDR because VDDR has a wide voltage level according to system configurations and applications. Its voltage level is 1.5V˜2.8V and can be either lower or higher than VDDH which has 1.8V˜2.5V. The wide voltage range of VDDR gives designer burden to decide the size of P3 and P4. Thus, another level shifter is needed to convert ENB voltage level from VDDR to VDDH.
FIG. 7 shows a prior art enable signal generator that converts the ENB voltage level from VDDR to VDDH. It has the same structure as FIG. 1 but VDDL is replaced with VDDR. START has the same voltage level as VDDR and it is delivered from the start-up signal in the system. FIG. 8 shows the timing diagram including START into FIG. 6.
Cross coupled logic enables to easily convert an input signal which has a wide voltage range to an output signal which has fixed voltage level. INV3 and INV4 (700, 702) are used to get complementary inputs from START. I/O devices should be used for INV3 and INV4 to prevent silicon break down because VDDR is higher than core voltage (VDDL). P10, P11, N10 and N11 (704-710) should be also I/O devices to avoid break down from VDDH.
Thirdly, another drawback of this design is that the VDDR power rail should be delivered into the macro block. The macro block is an independent circuit module which is reused to increase design efficiency. Normally, it has its own power domain. VDDR is used to generate complimentary inputs from START. Unfortunately, VDDR cannot typically be replaced with VDDH because of a leakage current from VDDH to ground. For example, if VDDR is lower than VDDH then both NMOS and PMOS of INV3 and INV4 are turned on simultaneously and leakage current flows from VDDH and ground. The usage of VDDR makes system level layout more complicated because of power rail delivery cross other macros.
Therefore, a need exists for an improved level shifting circuit and power sequence control design.